Peripheral Component Interconnect (PCI) Express is a computer expansion or laptop expansion bus standard, which is high-speed serial replacement of the older bus standards, such as, but not limited to PCI-X, Accelerated Graphic Port (AGP), and so forth. The PCI Express interface includes a signal detection circuit that may detect whether a valid analog signal has been received at one or more input pins. This operation is based on an assumption that a valid signal produces pulses that may exceed a voltage threshold over a long integration time. This may determine that a signal is a valid signal and not noise. The PCI express interface technology is under constant development and improvement. There are various generations of PCIe i.e. version 1.0a, 1.1, 2.0, 2.1, 3.0, 4.0 that has been released so far, based on their speed bins. Various versions of the PCIe differ from each other based on transfer rate and per-lane data rate. PCIe interface versions have various speed bins for transfer rate. Typically, the transfer rate is expressed in Gigatransfers per second (GT/s) or Gigabits per second (GT/s). The transfer rate of PCIe 1.0 and 1.1 is 2.5 GT/s per lane, for PCIe 2.0 and 2.1 is 5 GT/s per lane, for PCIe 3.0 is 8 GT/s per lane, and for PCIe 4.0 is 16 GT/s per lane.
The existing signal detecting techniques are based on level sensing and simple envelope integration and cannot detect a valid signal as speed approaches to 8 GT/s per lane or 16 GT/s per lane. Therefore, an operator or user opts to disable this function of signal detection and ignore it when speed approaches 8 GT/s or 16 GT/s per lane. Because of this limitation, existing signal detection techniques are being used only at slower speeds and initialization.
In light of above discussion and limitations of existing signal detection techniques, there exists a need for systems and methods for detecting signal at higher speeds.